(1) Field of the Invention
The present invention relates to a data sharing apparatus containing a memory and two processors of different endianness, as well as such processors for the apparatus, and particularly to data sharing between processors.
(2) Description of the Related Art
In the case where the basic word length of a processor is 2 bytes (16 bits) or more, there are two formats for byte ordering in storing data of 2 bytes or more into a memory, the so-called “big-endian” and “little-endian”. This is because the basic word length has 2 bytes or more, as opposed to the byte units in which addresses are assigned in a memory.
First, the big-endian format shall be explained.
Big-endian is a format for the ordering of a byte sequence (byte order) during the storage of data of 2 bytes or more, into a memory having byte unit addresses. It refers to the format that stores data in an ascending order of memory addresses, beginning with the byte at the big end (in other words, the Most Significant Bit (MSB) side. In this case, “B” should stand for byte, rather than bit). However, endian refers to byte sequence ordering and not to bit sequence ordering, so the order of bits within a byte does not change.
FIG. 1 is an explanatory diagram of the big-endian format. For example, in storing a 4 byte data ‘89ABCDEF’ (hexadecimal, hereinafter, the same for all within ‘ ’ marks) into the memory areas addressed 100 to 103 in the big-endian format, the data is stored as ‘89’, ‘AB’, ‘CD’, ‘EF’, sequentially, in the addresses 100 to 103.
FIG. 2 shows the same example as FIG. 1, only that it illustrates a memory image (memory data) having 32 bits as the basic word length. The memory address is in byte units, and the lower address (addressed byte position according to the least significant 2 bits of the address) within the basic word length is, from the left, “0”, “1”, “2”, “3”, in ascending order. The most significant byte ‘89’ is stored in the address “0”.
In this manner, in the big-endian format, data is stored into memory, in an ascending order of addresses, from the byte on the MSB-side.
FIG. 3 illustrates a typical structure for the connection of a big-endian-type CPU 2 and a memory 3b. A CPU is also simply referred to as a processor.
As shown in the same diagram, the input/output terminals D[31:24], D[23:16], D[15:8], D[7:0] of the CPU 2 are connected, respectively, to the lower addresses “0”, “1”, “2”, “3” of the memory 3b, via a data bus. As a result, byte data is stored, in an ascending order of memory addresses, starting from the MSB. Furthermore, in the memory 3b, a memory image of the case where a structure sample 4 is defined in a program for the CPU 2, is shown. A LONG INTEGER w is word data in the basic word length (32-bit) composed of the 4 bytes, w3, w2, w1, w0, in sequence from the MSB. The SHORT INTEGER x is half-word data, composed of x1, and x0, in sequence from the MSB. The same is true for a SHORT INTEGER y. CHAR a, b, c, and d, each represent byte data.
Next, the little-endian format shall be explained.
Little-endian refers to the format which stores data in an ascending order of memory addresses, from the byte on the little end (in other words, Least Significant Bit (LSB) side) first.
FIG. 4 is an explanatory diagram of the little-endian format. It shows the same data as in FIG. 1, where the 32-bit data ‘89ABCDEF’ is stored, sequentially, in the addresses 100 to 103, as ‘EF’, ‘CD’, ‘AB’, and ‘89’.
FIG. 5 illustrates a memory image of the same example in FIG. 4, with 32 bits as the basic word length. Compared to FIG. 2, the lower address sequence is inverted, with “0”, “1”, “2”, “3”, starting from the right.
FIG. 6 illustrates a typical structure for the connection of a little-endian-type CPU 1 and a memory 3a. As shown in the diagram, the input/output terminals D[7:0], D[15:8], D[23:16], D[31:24] of the CPU 1 are connected, respectively, to the lower address “0”, “1”, “2”, “3” of the memory 3a, via a data bus. As a result, byte data is stored, in an ascending order of memory addresses, starting from the byte on the LSB-side. Furthermore, in the memory 3a, a memory image of the case where a structure sample 4, the same as in FIG. 3, is defined in a program for the CPU 1, is shown. Compared to the memory image shown in FIG. 3, the byte sequence is in reverse.
As such, big-endian and little-endian are formats for byte sequence ordering, in storing data of 2 bytes or more into a memory, each having an opposite ordering sequence from the other.
Due to such incompatibilities, a structure that converts differences in endianness is necessary in order to preserve the identity of shared data in a system where a big-endian CPU and little-endian CPU co-reside.
Patent Document 1 (See Japanese Laid-open Patent Application No. 06-69978) discloses a packet communication apparatus including an endian conversion unit for converting packet data from a big-endian processor into the little-endian format, during packet communication between a big-endian CPU and a little-endian CPU.
In addition, Patent Document 2 (See Japanese Laid-open Patent Application No. 2000-3304) discloses a data alignment apparatus that performs a memory access by absorbing differences in data size, alignment, and endianness, through the conversion of data to be stored, based on the access address and access size.
However, in the technology disclosed in patent documents 1 and 2, it is necessary to add specialized hardware to processors equipped with an endian conversion unit. Moreover, since delays arise due to endian conversion, the technology poses a barrier to high speed memory access, even carrying with it the problem of hindering the speed of other processors, in the case where data is shared.
Furthermore, in general, image processing is carried out by big-endian processors, with communication being carried out by little-endian processors. With the inclusion of image processing functions in mobile phones in recent years, little-endian processors and big-endian processors have come to be connected to the same bus. This then creates a need for real-time sharing of data.